Huawei announced the τ scaling law at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS), proposing time scaling as a replacement for geometric scaling — a potential new path for chip and electronic system evolution. Under this time-scaling approach, Huawei introduced the LogicFolding architecture and revealed that its Kirin chip launching in fall 2026 will be the first to use it.
Traditional Moore’s Law relies on shrinking transistor dimensions, but advanced process nodes are hitting physical limits and diminishing returns. The core of τ scaling is systematically reducing signal and data propagation time across devices, circuits, chips, and systems to improve performance, energy efficiency, and equivalent transistor density.
At the device level, Huawei optimizes transistor and interconnect resistance and parasitic capacitance to lower the time constant τ. At the circuit level, LogicFolding breaks conventional layout boundaries, shortens critical path routing, and reduces RC load on signal propagation. At the chip level, Huawei uses software, architecture, and chip co-design to boost parallel efficiency. At the system level, the UnifiedBus interconnect protocol targets SuperPoD with unified memory addressing and native memory semantics to cut system communication latency.
Huawei claims it has already designed and mass-produced 381 chips using the τ scaling law over the past six years, covering smartphones and AI computing. The company expects its high-end chips designed under the law to reach 14 Å — equivalent to 1.4nm process transistor density — by 2031. For now, Huawei has only disclosed the design methodology and roadmap targets; it has not released independent performance benchmark data for LogicFolding on the Kirin chip.