AMD's sixth-generation EPYC processors (codenamed Venice) have started production on TSMC's 2nm node at the company's Taiwan fabs. They are the first high-performance computing (HPC) products built on TSMC's 2nm process. To address surging memory demands from agentic AI, AMD's follow-up Verano processors will also use 2nm and integrate LPDDR memory. TSMC's Arizona plant is slated for future production as well.
AMD is simultaneously investing over $10 billion in Taiwan's ecosystem, focusing on expanding advanced packaging capacity. The funds flow to packaging firms like ASE Technology Holding, SPIL (Siliconware Precision Industries), and PTI (Powertech Technology). Notably, PTI has completed the industry's first panel-level EFB (Elevated Fanout Bridge) 2.5D interconnect validation, which boosts interconnect bandwidth and power efficiency for Venice CPUs.
AMD's Helios rack-scale systems, combining Venice CPUs and Instinct MI450X GPUs, will be built by Sanmina, Wistron NeWeb, Wistron, and Inventec. The entire platform is expected to begin multi-gigawatt-scale deployment in the second half of 2026.